1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f8512c june 2001 rev. 13 eco #14322 pin configurations and block diagram features ?512kx8 bit cmos static ?random access memory ? access times 20 through 100ns ? data retention function (edi8f8512lp) ? ttl compatible inputs and outputs ? fully static, no clocks ?high density packaging ? 36 pin sip, no. 63 ? 32 pin dip, jedec pinout, no. 91 (55-100ns) ? 32 pin dip, jedec pinout, no. 183 (20-35ns) ?single +5v (10%) supply operation 20-55ns pin names the edi8f8512c is a 4096k bit cmos static ram based on four 128kx8 or 256kx4 (high speed) static rams mounted on a multi- layered epoxy laminate (fr4) substrate. functional equivalence to the monolithic four megabit static ram is achieved by utilization of an on-board decoder that interprets the higher order address(es) to select one of the128kx8 or 256kx4 static rams. the 32 pin dip pinout adheres to the jedec standard for the four megabit device, to ensure compatibility with future monolithics. a low power version with data retention (edi8f8512lp) is also available. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous, the edi8f8512c requires no clocks or refreshing for operation. 55-100ns 20-35ns 512kx8 static ram cmos, module description a?-a18 address inputs e chip enable w write enable g output enable dq?-dq7 common data input/output vcc power (+5v10%) vss ground nc no connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 nc vcc w dq2 dq3 dq0 a1 a2 a3 a4 vss dq5 a10 a11 a5 a13 a14 nc e a15 a16 a12 a18 a6 dq1 vss a0 a7 a8 a9 dq7 dq4 dq6 a17 vcc g 8f8512c pin config. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss 8f8512c pin config 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 a17 w a13 a8 a9 a11 g a10 e dq7 dq6 dq5 dq4 dq3 dq 0-7 128k x 8 128k x 8 128k x 8 128k x 8 a 0-16 w g a 17-a18 e decoder 8f8512c blk dia dq 4-7 256k x 4 256k x 4 256k x 4 256k x 4 a 0-17 w g a18 e decoder 8f8512c blk dia2 dq 0-3 fig. 1
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f8512c june 2001 rev. 13 eco #14322 absolute maximum ratings* recommended dc operating conditions dc electrical characteristics *typical: ta=25c, vcc=5.0v capacitance truth table (f=1.0mhz, vin=vcc or vss) ac test conditions (note: for tehqz,tghqz and twlqz, cl = 5pf) these parameters are sampled, not 100% tested. *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0c to +70c industrial -40c to +85c storage temperature -55c to +125c power dissipation 4 watts output current 20 ma parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 20-35ns 1ttl = 30pf 70-100ns 1ttl, cl =100pf g e w mode output power x h x standby high z icc2, icc3 h l h output deselect high z icc1 l l h read dout icc1 x l l write din icc1 parameter sym max unit address lines ci 30 pf data lines cd/q 43 pf chip enable line cc 10 pf write and output enable lines cw 32 pf parameter sym conditions min typ* max units [ 35 55 20-25 35 55-100 ns operating power icc1 w, e = vil, ii/o = 0ma, -- 340 70 570 390 130 ma supply current min cycle standby (ttl) power icc2 e vih, vin - vil dip -- 50 10 85 85 55 ma supply current vin vih sip -- -- -- -- -- 65 ma full standby power icc3 e vcc-0.2v c -- 5 2 40 40 5 ma supply current (cmos) vin vcc-0.2v or lp -- -- 40 -- -- 400 a vin [ 0.2v input leakage current ili vin = 0v to vcc -- -- -- 10 10 10 a output leakage current ilo v i/o = 0v to vcc -- -- -- 10 10 10 a output high voltage voh ioh=-1.0ma ( 70),or -4.0( [ 35) 2.4 -- -- -- -- -- v output low voltage vol iol = 2.1ma ( 70),or 8.0ma( [ 35) -- -- -- 0.4 0.4 0.4 v
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f8512c june 2001 rev. 13 eco #14322 ac characteristics read cycle read cycle 2 - w high symbol 20ns 25ns 35ns parameter jedec alt. min max min max min max units read cycle time t avav trc 20 25 35 ns address access time tavqv taa 20 25 35 ns chip enable access time telqv tacs 20 25 35 ns chip enable to output in low z (1) telqx tclz 3 3 3 ns chip disable to output in high z (1) tehqz tchz 10 12 15 ns output hold from address change tavqx toh 3 3 3 ns output enable to output valid tglqv toe 13 15 20 ns output enable to output in low z (1) tglqx tolz 0 0 0 ns output disable to output in high z(1) tghqz tohz 8 10 12 ns note 1: parameter guaranteed, but not tested. read cycle 1 - w high, g, e low fig. 2 fig. 3 address 1 address 2 tavav data 1 data 2 tavqv tavqx 8f8512c rd cyc1 a q tghqz telqv telqx e g q tehqz a tavav tglqv tglqx tavqv 8f8512c rd cyc2
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f8512c june 2001 rev. 13 eco #14322 ac characteristics read cycle symbol 55ns 70ns 85ns 100ns parameter jedec alt. min max min max min max min max units read cycle time t avav trc 55 70 85 100 ns address access time tavqv taa 55 70 85 100 ns chip enable access time telqv tacs 55 70 85 100 ns chip enable to output in low z (1) telqx tclz 5 5 5 5 ns chip disable to output in high z (1) tehqz tchz 30 30 35 40 ns output hold from address change tavqx toh 3 3 3 3 ns output enable to output valid tglqv toe 40 40 45 50 ns output enable to output in low z (1) tglqx tolz 0 0 0 0 ns output disable to output in high z(1) tghqz tohz 30 30 35 40 ns note 1: parameter guaranteed, but not tested. note 1: parameter guaranteed, but not tested. ac characteristics write cycle write cycle symbol 20ns 25ns 35ns parameter jedec alt min max min max min max units write cycle time t avav twc 20 25 35 ns chip enable to end of write telwh tcw 15 20 30 ns teleh tcw 15 20 30 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 15 20 30 ns taveh taw 15 20 30 ns write pulse width twlwh twp 15 20 25 ns twleh twp 15 20 25 ns write recovery time twhax twr 0 0 0 ns tehax twr 0 0 0 ns data hold time twhdx tdh 3 3 3 ns tehdx tdh 3 3 3 ns write to output in high z (1) twlqz twhz 0 10 0 12 0 15 ns data to write time tdvwh tdw 12 15 20 ns tdveh tdw 12 15 20 ns output active from end of write (1) twhqx twlz 3 3 3 ns
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f8512c june 2001 rev. 13 eco #14322 symbol 55ns 70ns 85n 100ns parameter jedec alt. min max min max min max min max units write cycle time t avav twc 55 70 85 100 ns chip enable to end of write telwh tcw 50 65 70 80 ns teleh tcw 50 65 70 80 ns address setup time tavwl tas 0 0 0 0 ns tavel tas 0 0 0 0 ns address valid to end of write tavwh taw 50 65 70 80 ns taveh taw 50 65 70 80 ns write pulse width twlwh twp 50 65 70 80 ns twleh twp 50 65 70 80 ns write recovery time twhax twr 0 0 0 0 ns tehax twr 0 0 0 0 ns data hold time twhdx tdh 0 0 0 0 ns tehdx tdh 0 0 0 0 ns write to output in high z (1) twlqz twhz 0 30 0 30 0 35 0 40 ns data to write time tdvwh tdw 30 30 35 40 ns tdveh tdw 30 30 35 40 ns output active from end of write (1) twhqx twlz 5 5 5 5 ns note 1: parameter guaranteed, but not tested. ac characteristics write cycle write cycle 1 - w controlled fig. 6 e a tavav telwh tavwh twlwh tavwl twhax w high z data valid twlqz twhqx tdvwh twhdx q d 8f8512c write cyc1
6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f8512c june 2001 rev. 13 eco #14322 write cycle 2 - e controlled fig. 7 a tavel high z tavav 8f8512c write cyc2 teleh e taveh tehax w twleh tehdx tdveh q data valid d
7 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f8512c june 2001 rev. 13 eco #14322 ordering information *read cycle time note 1: parameter guaranteed, but not tested. data retention characteristics lp 70-100ns only data retention e controlled characteristic sym test conditions vdd min typ max unit 70c 85c data retention voltage vdd vdd = 0.2v 2 -- -- -- v data retention quiescent current iccdr e > vdd -0.2v 2v -- 10 125 185 a vin > vdd -0.2v 3v -- 20 200 250 a chip disable to data retention time (1) tcdr or vin < 0.2v 0 -- -- -- ns operation recovery time (1) tr t avav* -- -- -- ns standard power speed package (ns) no. edi8f8512c20m6c 20 183 edi8f8512c25m6c 25 183 edi8f8512c35m6c 35 183 edi8f8512c70bsc 70 63 edi8f8512c85bsc 85 63 edi8f8512c100bsc 100 63 edi8f8512c55b6c 55 91 edi8f8512c70b6c 70 91 edi8f8512c85b6c 85 91 edi8f8512c100b6c 100 91 low power speed package with data retention (ns) leads edi8f8512lp70bsc 70 63 edi8f8512lp85bsc 85 63 edi8f8512lp100bsc 100 63 edi8f8512lp70b6c 70 91 edi8f8512lp85b6c 85 91 edi8f8512lp100b6c 100 91 note: to order an industrial grade product substitute the letter c in the suffix with the letter i, eg. edi8f8512c70b6c becomes edi8f8512c70b6i. fig. 8 vcc tr 8f8512c data retent. data retention mode e tcdr e vdd-0.2v vdd 4.5v 4.5v
8 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f8512c june 2001 rev. 13 eco #14322 package no. 63: 36 pin single-in-line package package no. 91: 32 pin dual-in-line package package no. 183: 32 pin dual-in-line package package description 8f8512c pkg 2 0.125 min 4.040 max. 0.020 0.016 0.575 0.565 0.150 max 0.100 35 x 0.100 =3.500 8f8512c pkg1 all dimensions are in inches 8f8512c pkg3 not recommended for new designs
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